[EE_CSIE] 非同步電路設計Lab1 - Wagging Shift Register

這是我們 非同步電路設計 Project / LAB1 ，用 Balsa 語言寫一個 Wagging Shift Register

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-- SRA1.balsa : Single Stage Shift Register
-- 20070515 by 9679505 / Amzshar Liu ( AaA )
import [balsa.types.basic]

procedure sra1(input i : byte ; output o : byte) is
variable x : byte
begin
loop
i -> x ; -- Input Communication
o <- x -- Output Communication
end -- end loop
end

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(-- SRC1.balsa : 1-place Shift Register (Improved)
i -> [x -> y] -> o
--)

import [balsa.types.basic]

procedure src1(input i : byte ; output o : byte ) is
variable x, y :byte
channel cl : byte
begin
loop
o <- y
i -> x ;
y := x
end -- end loop
end
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-- SRD1.balsa : demux i to o1, o2 alternately

--- 20070515 by 9679505 / Amzshar Liu ( AaA )
import [balsa.types.basic]

procedure srd1(input i : byte ; output o1 : byte ; output o2 : byte) is
variable x, y : byte
begin
loop
-- read channel i into register x while writing register y to channel o2
i -> x o2 <- y ;
-- read channel i into register y while writing register x to channel o1
i -> y o1 <- x
end -- end loop
end
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-- SRE1.balsa : demux i1, i2 into o alternately
-- 20070515 by 9679505 / Amzshar Liu ( AaA )
import [balsa.types.basic]

procedure sre1(input i1 : byte ; input i2 : byte ; output o : byte) is
variable x, y : byte
begin
loop
i1 -> x o <- y ;
i2 -> y o <- x
end -- end loop
end
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-- SRW8A.balsa: Multi-Stage Wagging Shift Register
-- 20070515 by 9679505 / Amzshar Liu ( AaA )
import [balsa.types.basic]
import [SRA1]
import [SRD1]
import [SRE1]

procedure srw8a(input i : byte ; output o : byte) is
constant n = 8
array 1..n/2 of channel c1, c2 : byte
begin
srd1(i, c1[1], c2[1])
sre1(c1[n/2], c2[n/2], o)
for i in 1..(n/2)-1 then
sra1(c1[i], c1[i+1])
sra1(c2[i], c2[i+1])
end -- end for
end

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-- SRW8C.balsa: Multi-Stage Wagging Shift Register
-- 20070515 by 9679505 / Amzshar Liu ( AaA )
import [balsa.types.basic]
import [SRC1]
import [SRD1]
import [SRE1]

procedure srw8c(input i : byte ; output o : byte) is
constant n = 8
array 1..n/2 of channel c1, c2 : byte
begin
srd1(i, c1[1], c2[1])
sre1(c1[n/2], c2[n/2], o)
for i in 1..(n/2)-1 then
src1(c1[i], c1[i+1])
src1(c2[i], c2[i+1])
end -- end for
end

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