[EE_CSIE] 台積新聞:台積公司推出全新40奈米及65奈米SPICE電路模擬工具認證機制

. 轉載自 http://www.tsmc.com/tsmcdotcom/PRListingNewsAction.do?action=detail&newsid=2641&newsdate=2008/04/22&language=E TSMC Unveils New 40/65-Nanometer SPICE Tool Qualification ProgramIncreases SPICE Modeling Accuracy and Simulation Performance for High Performance Chip Designs 台積公司推出全新40奈米及65奈米SPICE電路模擬工具認證機制 增加高效能晶片設計SPICE電路模擬的精確度及效率 Issued by: TSMC 發佈單位 :台積公司 Issued on: 2008/04/22 發佈日期 : 2008/04/22 Hsinchu, Taiwan, R.O.C. – April 22, 2008 - Taiwan Semiconductor Manufacturing Company, Ltd. (TSE: 2330, NYSE: TSM) today unveiled at its opening 2008 Technology Symposium a comprehensive SPICE Tool Qualification Program that drives its Design Service ecosystem partners to develop SPICE simulators with greater accuracy and higher performance. 台積公司今（22）日於美國矽谷舉行2008年第一場技術研討會，並在會中宣佈一個全備的SPICE電路模擬工具認證機制（SPICE Tool Qualification Program），進一步促進台積公司設計服務生態系統中的合作夥伴開發更高精確度及更高效率的SPICE電路模擬工具。 Targeting TSMC’s 65-, 40-nanometer (nm) and smaller geometry process technologies, the program’s benefits include improved device model accuracy, enhanced simulation efficiency, and compatibility across a wide selection of qualified SPICE simulators. The program also improves simulation accuracy, shortens transistor-level simulation cycle time, increases simulation capacity, and ultimately enables faster time-to-market and first time silicon success. 此一認證機制係針對65奈米、40奈米以及更先進的製程，能夠提昇元件模型精確度、強化模擬效率，並提供眾多通過認證且相容的SPICE電路模擬工具予客戶選擇。此外，此一機制亦能提昇電路模擬的精確度、縮短電晶體功能模擬的時間、增加電路模擬的處理量，因此最終能夠縮短客戶產品上市時程以及能夠促使首次晶片設計就能成功生產。 To address emerging nanometer effects associated with the 40nm technology and beyond, the company is introducing iSDK, interoperable SPICE Design Kit, together with the TSMC’s Model Interface (TMI), a new device modeling innovation and simulation performance improvement. Written in standard C language, iSDK with TMI is a new method for compact SPICE device modeling that is an addition to the traditional, and slower macro modeling approach. TSMC will provide iSDK through a common compiled shared library that will link directly to a vendors’ SPICE simulators. 為因應40奈米以及更先進製程所帶來的挑戰，台積公司推出結合了台積公司元件模型介面（TSMC Model Interface; TMI）的跨平台運作SPICE設計套件（Interoperable SPICE Design Kit; iSDK）；TMI是一個創新的元件模型模擬架構，能夠提高模擬的效率。相較於傳統、速度較慢且龐雜的模擬方法，結合了TMI的iSDK，是使用標準C語言編寫參數的全新方法，能使得電路模擬更為簡化。台積公司將與設計自動化工具(EDA)廠商建構資料庫共享平台，透過此一平台，晶片設計人員可以取得台積公司的iSDK，並直接連結到EDA廠商所提供的SPICE模擬工具進行模擬。 Once the SPICE simulator passes SPICE tool qualification TSMC will post a qualification report on TSMC-Online, the company’s customer only portal. Multiple EDA partners are already participating in the program including Agilent Technologies, Berkeley Design Automation, Cadence, Magma, Mentor, Simucad, and Synopsys. EDA廠商的SPICE模擬工具在通過台積公司此一機制認證後，台積公司就會在其客戶專屬的線上客戶服務系統（TSMC Online）公告相關驗證報告。目前已經有包括Agilent Technologies、Berkeley Design Automation、Cadence、Magma、Mentor、Simucad以及Synopsys等多家公司參與此一機制。 “TSMC is the first foundry to deliver on the commitment of providing more design accuracy by proactively working with multiple EDA vendors to create and qualify interoperability between SPICE simulation technologies and the foundry’s most advanced processes technologies,” said S.T. Juang, senior director, Design Infrastructure Marketing at TSMC. 台積公司設計建構行銷處資深處長莊少特表示：「台積公司領先專業積體電路製造服務領域，主動與多家EDA廠商合作，建立了一個整合SPICE模擬技術及最先進製程技術的跨平台運作機制，此一機制已經通過驗證，能夠成功提昇晶片設計的精確度。」 “Going beyond the traditional tool qualification program, TSMC’s Modeling Interface architecture sets a new standard in SPICE modeling accuracy and simulation efficiency. The program provides designers the ability to select qualified SPICE simulators to match their design needs, improve compliance with TSMC processes, and ensure design accuracy for first time silicon success,” he explained. 莊資深處長進一步表示：「不同於傳統的電路模擬工具驗證機制，台積公司創新的元件模型介面架構為SPICE模擬精確度及效率設立了新的標準。透過台積公司的SPICE電路模擬工具認證機制，晶片設計人員可以根據設計需求選擇最適當且經過驗證的電路模擬工具、進一步提高設計與台積公司製程的相容性，並且能夠確保設計的精確度，使得首次晶片設計就能成功生產。」 台積公司今年在美國舉辦的技術研討會分別於美國時間4月22日在加州聖荷西、4月25日在麻塞諸塞州波士頓以及4月28日在德州奧斯汀舉行。此外，今年內台積公司也將陸續在台灣、日本及歐洲等地舉辦技術研討會。欲參加任一技術發研討會者，請至台積公司網站(www.tsmc.com)首頁報名。 About TSMC Active Accuracy Assurance Initiative 關於台積公司AAA-主動精準保證 (Active Accuracy Assurance Initiative; AAA) 機制 The TSMC AAA initiative is a broad-based program that encompasses all components of the design ecosystem. It provides standards of accuracy to all TSMC partners, including EDA tool suppliers, IP providers, library developers, and Design Center Alliance (DCA) partners. TSMC applies the same standards to tools, building blocks, and technologies, including TSMC Reference Flow 8.0, design for manufacturing (DFM) tools, process design kits (PDK), design support and backend services. 台積公司的AAA-主動精準保證機制是一個全面性的計畫，涵蓋所有設計生態環境中的環節，提供精確度標準給所有合作夥伴，包括電子設計自動化工具、矽智財及資料庫以及設計服務聯盟合作夥伴。此外，台積公司也以相同標準應用於自身的工具、矽智財及資料庫及技術，包括設計參考流程8.0版、可製造性設計工具、製程設計套件，以及設計支援及後段服務等。 About TSMC 關於台積公司 TSMC is the world’s largest dedicated semiconductor foundry, providing the industry’s leading process technology and the foundry industry’s largest portfolio of process-proven libraries, IP, design tools and reference flows. The Company’s total managed capacity in 2007 exceeded eight million (8-inch equivalent) wafers, including capacity from two advanced 12-inch Gigafabs, four eight-inch fabs, one six-inch fab, as well as TSMC’s wholly owned subsidiaries, WaferTech and TSMC (Shanghai), and its joint venture fab, SSMC. TSMC is the first foundry to provide 40nm production capabilities. Its corporate headquarters are in Hsinchu, Taiwan. For more information about TSMC please see http://www.tsmc.com . 台積公司是全球最大的專業積體電路製造服務公司，提供業界卓越的製程技術、以及業界最完備並且通過製程驗證的元件資料庫、矽智材、設計工具以及設計參考流程。民國九十六年所管理的總產能超過800萬片約當八吋晶圓，包括來自兩座最先進的十二吋超大型晶圓廠(晶圓十二及十四廠)、四座八吋晶圓廠(晶圓三、五、六及八廠)、一座六吋晶圓廠(晶圓二廠)，以及來自轉投資子公司美國WaferTech公司、台積電(上海)有限公司以及新加坡合資SSMC公司充沛的產能支援。台積公司係第一個推出40奈米製程的專業積體電路製造服務公司。進一步資訊請至公司網站http://www.tsmc.com.tw 查詢。